1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a technique of forming a self-aligned contact, and to a method of fabricating a semiconductor device having a self-aligned contact formed by such a technique.
2. Description of the Related Art
As semiconductor devices become smaller and smaller, the line width and the spacing between lines of the devices decrease. The resolution of a lithographic process used to form the lines of the semiconductor device must be increased to provide a smaller line width and spacing. However, the precision of an alignment technique, carried out to facilitate the lithographic process, can not be increased to comport with the increased resolution used to produce the fine line width and line spacing demanded of today""semiconductor devices. Accordingly, any misalignment during the fabrication of semiconductor must be minimized if a reduction in the size of semiconductor devices is to be achieved.
In the case of a semiconductor memory device, such as a dynamic random access memory (DRAM) including a capacitor, the capacitor is formed after a bit line is formed. A buried contact (BC) pad for electrically connecting the source/drain region of a transistor to the storage electrode of the capacitor is formed after the bit line is formed. A long and deep contact hole, i.e., a contact hole having a high aspect ratio, is required to form the BC pad. However, it is not easy to secure an alignment margin sufficient for a lithographic process to produce a contact hole having a high enough aspect ratio. In particular, an alignment margin can not be secured for a design rule of 0.20 xcexcm or smaller.
Recently, a technique of forming a self-aligned contact hole has been mainly used in connection with the forming of a BC pad. In this technique, a contact hole is formed by depositing an insulation layer on a lower conductive layer, and performing an etching process using the lower conductive layer and the insulation layer as a mask. This method will be described below with reference to FIGS. 1-5.
FIG. 1 shows the layout of a photoresist layer pattern used as an etching mask in the conventional method of forming a self-aligned contact. FIGS. 2 through 5 are sectional views taken along the line I-Ixe2x80x2 of FIG. 1 and show the progression of the conventional method of forming a self-aligned contact.
In FIG. 1, reference numeral 100 denotes an active mask window for defining an active region and a field region. Reference numeral 110 denotes a gate mask window used for forming a gate stack pattern. Reference numeral 120 denotes a bit line mask window used for forming a bit line pattern. Reference numeral 130 denotes a photoresist layer pattern serving as an etching mask used for forming a self-aligned contact hole.
Referring to FIG. 2, isolation regions 210 defining active regions 205 are formed as trenches in a semiconductor substrate 200 using the active mask windows (100 in FIG. 1). A conductive film pad 220 is formed on each of the active region 205. A first interlayer insulation layer 230 is formed to completely cover the conductive film pads 220. Next, bit line stacks 240 are formed on the first interlayer insulation layer 230 using the bit line mask windows (120 in FIG. 1). Each of the bit line stacks 240 is formed by sequentially forming a barrier metal layer 241, a bit line conductive layer 242 and a bit line capping layer 243 one upon the other. Subsequently, bit line spacers 250 are formed on the sidewalls of each of the bit line stacks 240.
Referring to FIG. 3, a second interlayer insulation layer 260 is formed to completely cover the bit line stacks 240 and the bit line spacers 250. Subsequently, the second interlayer insulation layer 260 is planarized such that the second interlayer insulation layer 260 has a predetermined thickness at the bit line stacks 250.
Referring to FIG. 4, a photoresist film pattern 130 is formed on the second interlayer insulation layer 260. The photoresist film pattern 130 is formed such that only those portions of the second interlayer insulation layer 260 between the bit line stacks 240 are exposed, and the remaining portions of the second interlayer insulation layer 260 are covered, as is also well shown in FIG. 1. After the photoresist film pattern 130 is formed, the second interlayer insulation layer 260 and the first interlayer insulation layer 230 are etched using the photoresist film pattern 130 as an etching mask. As a result, contact holes 270 exposing the top surfaces of the conductive film pads 220 are formed, as shown in FIG. 5. Conductive plugs (not shown) can be formed by filling the contact holes 270 with conductive material.
As the integration density of semiconductor devices increases, it becomes more difficult to etch the insulation layers to form the contact holes 270 due to the accumulation of polymer. Thus, the amount of polymer generated during the etching process must be somehow limited to prevent the etching process from stopping prematurely. However, reducing the amount of polymer that will be generated is accompanied by a reduction in the selection ratio with respect to the bit line spacers 250 formed of silicon nitride. Therefore, when this countermeasure is taken, the bit line spacers 250 will be etched when the mask 130 is even slightly misaligned. When the bit line spacers 250 are over-etched, the bit line conductive layer 242 may be exposed, as shown at part A in FIG. 5. As a result, the conductive plug filling the contact hole will directly contact the bit line conductive layer 242, whereby the lower electrode of a capacitor and the bit line are short-circuited.
A first object of the present invention is to solve the above-described problems by providing a method of forming a self-aligned contact characterized by an alignment margin sufficient to prevent a short from being created between adjacent conductive layers.
To achieve this object, the present invention provides a method in which gate stacks are formed in a striped pattern on a semiconductor substrate, gate spacers are formed on the sidewalls of the gate stacks, conductive film pads serving as buried contact pads are formed between the gate spacers, a first interlayer insulation layer is formed on the conductive film pads and the gate stacks, bit line stacks are formed on the first interlayer insulation layer in a striped pattern extending crosswise relative to the striped pattern of the gate stacks, bit line spacers are formed on the sidewalls of the bit line stacks, a second interlayer insulation layer is formed on the first interlayer insulation layer in such a way that the upper surfaces of the bit line stacks are exposed, and a photoresist film pattern is formed on the second interlayer insulation layer in a striped pattern parallel to the striped pattern of the gate stacks. The photoresist film pattern exposes segments of the bit line stacks and portions of the second interlayer insulation layer disposed directly above respective ones of the conductive film pads. Contact holes exposing the conductive film pads are formed by etching the second interlayer insulation layer and the first interlayer insulation layer using the photoresist film pattern, the bit line stacks and the bit line spacers as etching masks. The conductive plugs contacting the conductive film pads are formed by filling the contact holes with a conductive material.
Preferably, each of the gate stacks includes a gate insulation layer, a gate conductive layer and a gate capping layer which are sequentially formed one atop the other on the semiconductor substrate, and each of the bit line stacks includes a barrier metal layer, a bit line conductive layer and a bit line capping layer which are sequentially formed one atop the other on the first interlayer insulation layer.
The second interlayer insulation is preferably formed by covering the first interlayer insulation layer and the bit line stacks with a layer of insulating material, and completely planarizing the layer, i.e., until the upper surfaces of the bit line stacks are exposed. The planarization may be performed using chemical mechanical polishing.
The conductive plug is preferably formed by depositing enough conductive material to fill the contact holes and cover the bit line stacks, and planarizing the result to expose the upper surfaces of the bit line stacks. The planarization may be performed using an etch back technique or chemical mechanical polishing.
Another object of the present invention is to provide a semiconductor device that is also free of the above-described problems of the prior art.
To achieve this object, the technique of forming a self-aligned contact as summarized above is incorporated into an overall method of manufacturing a semiconductor device as follows. After the conductive plugs are formed, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are sequentially formed on the conductive plugs, the bit line stacks and the second interlayer insulation layer. A second photoresist film pattern is then formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask, this etching terminating when the etch stop layer is reached (exposed). Next, the second photoresist film pattern is removed. Second contact holes for use in forming capacitor lower electrodes are themselves formed by sequentially removing the exposed portions of the etch stop layer and third interlayer insulation layer using the hard mask layer as an etching mask. In this way, the second contact holes expose the conductive plugs.
The second contact holes are filled with a conductive material to form capacitor lower electrodes contacting the conductive plugs.
Preferably, the etch stop layer is formed of a material having an etching selection ratio with respect to the oxide layer. In particular, the etching stop layer is preferably a silicon nitride layer. The third interlayer insulation layer is preferably formed of a material having an etching selection ratio with respect to the etch stop layer.